Robustness of the transistors to voltage stress, output power, and/or efficiency may be relevant parameters in the design of amplifiers such as, e.g., power amplifiers (PA). The required output power may need to be achieved without overstressing the transistors, in order to keep their characteristics unchanged during the desired product lifetime. This should be done while maximizing the PA efficiency, which is the ratio of the output power to the power consumption. Negative effects of high power consumption may be low battery lifetime and/or high self-heating of the PA.
Other relevant parameters for the PA performance may be saturation power (Psat) and sharpness of the transition from linear operation to saturation (in the AM/AM (amplitude-to-amplitude modulation) characteristic). High Psat and sharp transitions may make it easier to obtain low ACLR (Adjacent Channel Leakage Power Ratio) and low EVM (Error Vector Magnitude) of the transmitted signal. Unfortunately, CMOS (Complementary Metal Oxide Semiconductor) PAs usually show relatively smooth transitions.
While too high voltage stress may lead to device degradation or even to total failure, not using the full voltage stress capability of the transistors normally hinders the maximization of Psat and of the efficiency. Unfortunately this may often be the case, since the circuits may need to be designed with enough headroom, taking into account the variations over process, voltage and temperature (PVT), in order to prevent overstress under worst case conditions.
Dynamic biasing techniques may be used in order to sharpen the relatively smooth transition from linear operation to saturation of CMOS PAs and even to increase Psat.
Higher input voltage stress can be endured by using more robust transistors (thick oxide gate) at the input of the PA output stage. However, PA performance may decrease significantly since thick oxide transistors are typically slower than thin oxide transistors.
Relatively low variation of the input voltage over PVT may be accomplished by a voltage-mode driving circuit whose output voltage saturates to a well-controlled value. This technique has the disadvantage of the (CMOS) driving circuit also having a smooth transition from linear operation to saturation, which may add to the one of the output stage.
It may thus be desirable to maximize the input voltage of an amplifier stage, e.g. an amplifier output stage such as, e.g., a CMOS PA output stage, while preventing overstress under worst case conditions and considering the requirement of a sharp transition from linear operation to saturation.